Penalty free address decoding scheme

ABSTRACT

The present invention relates to an arrangement for addressing a dual-plane memory. The memory has a first signal input used to activate the memory and a second signal input used to address one of the two memory planes. The arrangement comprises a microprocessor that comprises a chip-select generator having a first chip-select output and a second chip-select output. The first output is connected to the first input of the memory and the second output is connected to the second input of the memory. The outputs and the inputs are connected to each other without time critical element in-between.

TECHNICAL FIELD OF THE INVENTION

The present invention relates to arrangements and methods for change-over between memory planes when updating a program memory.

DESCRIPTION OF RELATED ART

When designing products which contain a microcontroller, software SW for this microprocessor has traditionally been contained in either on-chip ROM or off-chip (i.e. separate) erasable EPROM. Recent years, Flash FPROMs has been used to store the SW because FPROMs can be reprogrammed to update the SW in the product. The product can be designed in such a way that it can reprogram itself e.g. via a serial cable, Internet connection or similar. The problem with this self-programming is that the microcontroller can not execute SW located in the FPROM, while the FPROM is being reprogrammed.

This problem can be addressed by copying the update algorithm to RAM and executing it from the RAM, keeping the update algorithm in on-chip ROM or off-chip ROM/EPROM or by using two different FPROMs. In this way the microcontroller can execute code from one FPROM, while updating the contents of the other FPROM.

The later solution also has the advantage that two versions of the application software can be kept at the same time, and if problems arise with the new version, the product can automatically revert to the previous version, and do a new update. In many products the space is limited (e.g. mobile phones) and therefore two FPROM chips are inconvenient. The FPROM chip vendors have addressed the problem by launching the “dual-plane” architecture, which is two independent FPROM chips on the same die. This dual architecture allows one part of the FPROM to be used for program execution while the other part is being erased or reprogrammed.

The two “planes” share all control, data and addresses pins, and are usually mapped into separate address spaces of the chip. This address distribution implies that the SW has to be compiled/linked to a specific FPROM plane. If a particular version of the SW has been linked for a first address space, it will not be able to work correct in a second address space, and vice versa. This restriction is in general not acceptable, and therefore auxiliary hardware is needed to swap the address-spaces of the two FPROM planes, such that the “active”, i.e. currently used, plane always is mapped into one address space and the passive FPROM plane into the other. It is known to use a general purpose I/O pin in conjunction with an XOR gate to toggle the value of the most significant address pin of the FPROM. This address bit of the FPROM distinguishes the two planes of the dual-plane FPROM. Therefore the I/O pin can make either one of the two planes to “switch places” in the memory map of the microcontroller. In the U.S. Pat. No. 6,192,421 is disclosed a program-controlled device with reloading possibility for and change-over possibility to a second operating system without program interruption, where a switchable change-over switch is provided in the address lines. In the US patent however, the switchable change-over switch provided in the address lines causes an additional delay, which causes general performance degradation.

If the microcontroller has a programmable chip-select generator, the problem of swapping the FPROM planes can be solved in the following way: Two separate chip-select lines are programmed to activate on one FPROM plane each. The two chip-select lines are OR'ed together to form the resulting chip select signal for the FPROM, while one of the chip-select signals also are connected to the most significant address line of the FPROM. The problem with this solution is that the resulting chip select signal of the FPROM usually is on the critical path, and the delay inferred on this signal by the OR-gate causes general performance degradation.

SUMMARY OF THE INVENTION

The present invention relates to a problem how to change-over between memory planes without performance degradation caused by delay on time critical paths between a microcontroller controlling the memory, and the memory.

A purpose with the invention is to accomplish execution of program code in the memory, while the memory is reprogrammed.

The problem is solved by the invention by a microcontroller comprising a chip-select generator, which is used in a way that no time-critical elements need to influence time-critical paths between the microcontroller and the controlled memory.

More in detail, the problem is solved by an arrangement for addressing the memory, which memory is a dual-plane memory having a first signal input used to activate the memory and a second signal input used to address one of the two memory planes. The arrangement comprises a microprocessor having a built-in configurable chip-select generator with a first chip-select output and a second chip-select output. The first output is connected to the first input of the memory and the second output is connected to the second input of the memory. The outputs and the inputs are connected to each other without time critical element in-between.

One advantage with the invention is the possibility to download a new version of software to a product, without performance has to be compromised.

Another advantage with the invention is that software can be compiled/linked in the same way, no matter if it is downloaded to a first or second plane in the memory, and without performance has to be compromised.

Yet another advantage with the invention is that it accomplish high performance, without increasing the component cost.

The invention will now be described more in detail with the aid of preferred embodiments in connection with the enclosed drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a block schematic illustration of a memory configuration according to the invention, comprising a microprocessor controlling a dual-plane memory.

FIG. 2 shows a memory map comprising two planes of the dual-plane memory, each of which plane is either active or inactive.

FIG. 3 shows a flow chart illustrating a method used to program the microprocessor in accordance with the invention when the polarity of CS1 is changeable.

FIGS. 4 a and 4 b show flow chars illustrating methods used to program the microprocessor in accordance with the invention when the polarity of CS1 is fixed.

DETAILED DESCRIPTION OF EMBODIMENTS

FIG. 1 discloses a memory configuration according to the invention. The figure shows a microprocessor MP connected to a dual-plane Flash Programmable Read Only Memory FPROM. The FPROM can be programmed or re-programmed after the chip has been soldered onto a chip-board. The FPROM comprises a first signal input CS used to activate the memory and a second signal input A19, which is an address input, used to address either one of two planes of the dual-plane memory. In this example, activation of the address input A(19) represents activation of the nineteenth address bit. The FPROM comprises data access lines D(31:0) and address input lines A(18:0). The build up of the FPROM will be further clarified when the next figure in the patent application is explained. The microprocessor comprises an external bus interface EBI. The bus interface generates signals that control the access to the FPROM. The bus interface EBI comprises a first chip-select output CS0 and a second chip-select output CS1. The first output CS0 of the microprocessor is connected to the first input CS of the FPROM. The second output CS1 of the microprocessor is connected to the second input A19 of the FPROM. The external bus interface EBI is configurable and can be programmed to activate the outputs CS0 and CS1 under predetermined conditions. The microprocessor in FIG. 1 comprises nineteen address output lines A(20:2) and thirty-two data access lines Dt(31:0). The address output lines A(20:2) of the microprocessor are connected to the address input lines A(18:0) of the FPROM. The data access lines Dt(31:0) of the microprocessor are connected to the data access lines D(31:0) of the FPROM.

FIG. 2 shows, as an example, a memory map used in the configuration shown above. The figure shows hexadecimal notation of addresses and from now on all addresses will be referred to in the patent description by hexadecimal notation. The full content of the memory map extends from address 00.0000 to address 100.0000. It is to be noted that the memory map shown in FIG. 2 is the memory map that is seen by the microprocessor MP. A static random access memory SRAM is located between address 40.0000 and 60.0000 of the memory map. The random access memory function as a working memory for the microprocessor MP. The memory map I/O MMIO starting from address 00.0000 is used to store input/output interface parameters used by the microprocessor. The FPROM that was shown in FIG. 1 is a so-called dual-plane FPROM that is two independent FPROM chips on the same die. This architecture allows one part of the FPROM to be used for program execution while the other part is being erased or reprogrammed. The two planes share all control, data and addresses pins, and are usually mapped into separate address spaces of the chip. E.g. a dual-plane chip of 4 Mbit+4 Mbit FPROM looks like an 8 Mbit FPROM chip to the external world. The two planes are mapped into the lower and upper halves of the address space, respectively. The FPROM can also have uneven splits, e.g. 2 Mbit+6 Mbit. The location of the two planes in the memory map in this example is disclosed in FIG. 2. A first plane FP0 is located from address 80.0000 to BF.FFFF. A second plane FP1 is located from address C0.0000 and FF.FFFF.

The above shown address distribution of the FPROM implies that the software has to be compiled/linked to a specific FPROM plane. If a particular version of the software has been linked for the FP1 plane, it will not be able to work correct in the FP0 plane, and vice versa. This restriction is in general not acceptable, and therefore the address-spaces need to be swapped, such that the currently used plane, the so-called active plane, always is mapped into one address space (e.g. 80.0000-BF.FFFF). The currently not used plane, the so-called passive FPROM plane, is in the same way mapped into the other address space (e.g. C0.0000-FF.FFFF).

To always access the “correct” plane, the invention makes use of the external bus interface EBI located in the microprocessor MP. The external bus interface comprises in this example a built-in programmable chip-select generator. The chip-select generator has the ability to assert more than one output at the same time. This ability is present on some off-the-shelf micro-controllers, e.g. ATMEL AT91M40800.

According to the invention, the chip-select generator is configured to always activate the first chip-select output CSO whenever the FPROM is to be accessed. Assuming now that FP0 is the plane currently used, i.e. the active plane. Beyond CSO, also CS1 is activated (active “low”). The address range 80.0000 to BF.FFFF is now accessed. If on the other hand FP1 instead is defined to be the plane currently used, i.e. FP1 is the active plane, the chip-select generator is re-programmed to change the polarity of CS1. CS1 now becomes inactive (or active “high”) when the FPROM is to be accessed. In this case the address areas C0.0000 to FF.FFFF will be accessed. In the figure can be seen how the chip-select signals CS0 and CS1 are used to access the planes. When CSO is activated the memory area MO is activated. If also CS1 is activated the area M1 is activated and FP0 is selected. If CS1 instead is inactivated, FP1 is selected.

In FIG. 3 is disclosed a flow chart showing some of the steps used when the chip-select generator is programmed in accordance with the invention and when it is possible to program the generator to change the polarity of CS1. The flow chart is to be read together with the earlier shown figures. The steps are as follows:

-   -   CS0 is programmed to be active “low” covering M0 when accessing         the memory. This step is shown in the figure by a block 101.     -   After definition of which memory plane FP0 or FP1 that is the         active plane, the programming of CS1 starts. This step is shown         in the figure by a block 102.     -   If FP0 is defined as the active plane, CS1 is programmed to be         active “low” covering Ml. This step is shown in the figure by a         block 103.     -   If on the other hand FP1 is defined as the active plane, CS1 is         programmed to be active “high” covering M1. This step is shown         in the figure by a block 104.

The way to program the chip-select generator of course contains a manifold of different variations depending on which type of chip select generator that is used. In the micro-controller ATMEL AT91M40800 for example, the chip-select output CS1 referred to above is fixed to be either active “high” or active “low”. If the chip-select generator is not able to reprogram the polarity of its outputs, CS1 can be reprogrammed to react on the address range instead. If for example CS1 is fixed active “low” it is possible to change polarity by changing the address area in which CS1 is active. Changing base address for desired plane can do this. A description of this can be found in the description of the microcontroller AT91M40400, Rev. 0768B-09/98. The address range which the chip-select outputs respond to can usually be programmed by writing to a single register. In this way the WRITE operation is atomic and this property solves all problems with consistency of the chip-select logic.

In FIG. 4 is disclosed a flow chart showing some of the steps used when the polarity of CS1 is fixed. The first two blocks 101&102 of FIG. 4 a and 4 b are the same as the blocks 101&102 already shown in FIG. 3. The flow chart is to be read together with also the earlier shown figures. The steps in FIG. 4a where CS1 is fixed active “low” are as follows:

-   -   If FP0 is defined as the active plane and CS1 is fixed active         “low”, CS1 is programmed to cover Ml by programming the address         range 80.0000-BF.FFFF which the chip-select outputs respond to.         This step is shown in the figure by a block 105.     -   If on the other hand FP1 is defined as the active plane and CS1         is fixed active “low”, CS1 is programmed to cover M0/M1 i.e. the         part of M0 which is not covered by M1, by programming the         address range C0.0000-BF.FFFF which the chip-select outputs         respond to. This step is shown in the figure by a block 106.

The steps in the flow chart in FIG. 4 b where CS1 is fixed active “high” are as follows:

-   -   If FP0 is defined as the active plane and CS1 is fixed active         “high”, CS1 is programmed to cover M0/M1 by programming the         address range C0.0000-BF.FFFF which the chip-select outputs         respond to. This step is shown in the figure by a block 107.     -   If on the other hand FP1 is defined as the active plane and CS1         is fixed active “high”, CS1 is programmed to cover M1 by         programming the address range 80.0000-BF.FFFF which the         chip-select outputs respond to. This step is shown in the figure         by a block 108.

Different variations are of course possible within the scope of the invention. The invention can for example be implemented by ASIC-design, ASIC: Application Specific Integrated Circuits. The chip-select generator can be externally located outside the microprocessor. The technique to program the configurable chip-select generator varies depending on which type of chip select generator that is used. The invention is of course not limited to the above described and in the drawings shown embodiments but can be modified within the scope of the enclosed claims. 

1-7. (Canceled)
 8. An arrangement for addressing a dual-plane memory, said memory having a first memory plane, a second memory plane, a first signal input that activates the memory, and a second signal input that selectively addresses either the first or second memory plane, said arrangement comprising: a microprocessor that includes a chip-select generator, said chip-select generator including: a first chip-select output connected to the first signal input of the dual-plane memory; and a second chip-select output connected to the second signal input of the dual-plane memory; wherein the first and second chip-select outputs are connected to the first and second signal inputs without a time-critical element in-between.
 9. The arrangement of claim 8, wherein the chip-select generator is built into the microprocessor.
 10. The arrangement of claim 8, wherein the chip-select generator is configurable.
 11. The arrangement of claim 8, wherein either the first or second memory plane is defined as an active plane, and the second chip-select output is arranged to selectively address either the first or second memory plane, depending upon which of the two memory planes is defined as the active memory plane.
 12. The arrangement of claim 11, wherein the second chip-select output is active “low” when the first memory plane is defined as the active memory plane, and the second chip-select output is active “high” when the second memory plane is defined as the active memory plane.
 13. The arrangement of claim 11, wherein the first and second memory planes are reprogrammable Flash Programmable Read Only Memories (FPROMs), and the microprocessor is arranged to erase or reprogram the inactive memory plane while the active memory plane is used for program execution.
 14. The arrangement of claim 8, wherein the second chip-select output is programmed to react on a specified address range.
 15. The arrangement of claim 8, wherein the first chip-select output is active “low” when the dual-plane memory is accessed.
 16. The arrangement of claim 8, wherein the chip-select generator is implemented on an External Bus Interface (EBI) of the microprocessor, which simultaneously asserts the first and second chip-select outputs.
 17. A method of controlling a dual-plane memory having a first memory plane and a second memory plane, said method comprising the steps of: connecting a microprocessor to the dual-plane memory, said microprocessor including a chip-select generator on an external bus interface; generating by the chip-select generator, a first chip-select output and a second chip-select output; connecting the first chip-select output to a first signal input of the dual-plane memory, said first signal input selectively activating the dual-plane memory by switching between a high and a low parity; connecting the second chip-select output to a second signal input of the dual-plane memory, said second signal input selectively addressing either the first or second memory plane by switching between a high and a low parity; whereby the first and second chip-select outputs are connected to the first and second signal inputs without a time-critical element in-between.
 18. The method of claim 17, wherein the step of generating the first chip-select output and the second chip-select output includes simultaneously generating the first and second chip-select outputs by the chip-select generator.
 19. The method of claim 17, wherein the first and second memory planes are reprogrammable Flash Programmable Read Only Memories (FPROMs), and the method further comprises erasing or reprogramming the second memory plane while the first memory plane is used for program execution. 